Capacitors are more easily implemented in silicon on insulator (SOI) wafers than in bulk silicon wafers when linearity of the capacitance value with respect to the applied voltage is desired. These linear capacitors can be made by implanting high dose phosphorus into silicon and using the thin gate oxide as the capacitor dielectric. The linear capacitors made on SIMOX (separation of silicon by implantation of oxygen) SOI wafers however are often leaky and prone to failure under voltage ramp break-down testing. The electrical breakdown strength of the dielectric oxide is low in the SIMOX wafers and the SIMOX capacitor yield is low compared with those made on bulk silicon wafers. Defects created by implant damage at high dose and gettering of heavy metal by high concentration of phosphorus promote weak spots in the thin oxide dielectric. These weak spots further cause the failure mechanism of these linear capacitors.
In addition, certain applications also require that the linearity be maintained over a wide range of temperatures, for example 25 to 300 degrees C. so that the capacitors may be used in high temperature applications.
Thus a need exists for a linear SOI capacitor having suitable voltage breakdown characteristics and which may also be used in high temperature applications.